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XMEGA A [MANUAL]
8077I–AVR–11/2012
corresponding CCx register act like a FIFO. When the CC register is empty or read, any content in the buffer register is
passed to the CC register. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional
interrupt.
Figure 14-5. Capture double buffering.
Both the CCx and CCxBUF registers are available as an I/O register. This allows initialization and bypassing of the buffer
register and the double buffering function.
14.6
Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each
timer/counter clock input.
14.6.1 Normal Operation
In normal operation, the counter will count in the direction set by the direction (DIR) bit for each clock until it reaches TOP
or BOTTOM. When up-counting and TOP is reached, the counter will be set to zero when the next clock is given. When
down-counting, the counter is reloaded with the period register value when BOTTOM is reached.
Figure 14-6. Normal operation.
As shown in Figure 14-6, it is possible to change the counter value when the counter is running. The write access has
higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed
during normal operation.
Normal operation must be used when using the counter as timer base for the capture channels.
14.6.2 Event Action Controlled Operation
The event selection and event action settings can be used to control the counter from the event system. For the counter,
the following event actions can be selected:
Event system controlled up/down counting
BV
"capture"
IF
CNT
CCxBUF
CCx
EN
"INT/DMA
request"
data read
CNT
BOTTOM
MAX
"update"
TOP
CNT written
DIR
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